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Digital Design Verification Engineer

  • Location:


  • Contact:

    Rebeca Martens

  • Job type:


  • Contact phone:

    +32 15 28 40 47

  • Industry:

    Technology, Hardware

  • Contact email:

Are you looking for an challenging project as an freelance Digital Design Verification Engineer at a leading provider of standard and custom integrated circuits (ICs) that power Industrial IoT applications? Would you like to work in an innovative environment where they work on battery management, bluetooth® low energy, Wi-Fi? Don't wait any longer and take your chance!


  • Participate in feasibility studies
  • Develop verification plan based on specifications
  • Review design specifications to improve their quality, i.e. fitness for verification
  • Prove correctness of design against specification
  • Design and develop verification systems, decomposition and hardware/software partitioning
  • Develop verification components
  • Optimize solutions for key indicators such as reusability, performance and ease of use
  • Identify and communicate improvements that may ease verification and/or improve design behaviour
  • Participate and consult in design reviews
  • Support design engineers in verification related activities
  • Review and develop documentation templates, and document work properly
  • Schedule tasks and report progress to project leader
  • Take ownership of verification environments for assigned blocks, and tools appointed to you as Expert User.

Do the above responsibilities fit you like a glove?
Upload your CV and motivation letter via the "apply now" button and you can expect feedback from us soon.
If something is not entirely clear, you can reach out to us by telephone of course.


  • 5+ years of relevant working experience in digital design verification
  • Intermediate digital design skills
  • Knowledge of verification methodologies, platforms and techniques, i.e. Functional Verification, ABV, Formal Verification, regression frameworks, UVM, FPGA
  • Experienced with Cadence Xcelium, eManager+vManager, Verilog, VHDL, System-Verilog
  • Able and experienced in independently setting up a UVM testbench from scratch, from specification to verification report
  • Applies advanced methods to complex problems and demonstrates understanding of interfaces with other disciplines
  • Ability to propose innovative and leading edge solutions
  • Highly proficient in English language, written and spoken
  • Must have good interpersonal communication skills and customer focus
  • Ability to convince others based on technical knowledge and shows assertiveness to inform superiors/peers
  • Team player with a positive attitude who drives, develops and tutors colleagues within own discipline
  • Ability to set and meet goals and deadlines for self and others


  • A balanced salary package based on your capabilities and experience.

Existing right to work in Europe required ( please read job spec in full before applying ).

Vacancy number : 17476